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RDA5807SP
SINGLE-CHIP BROADCAST FM RADIO TUNER
1 General Description
Rev.1.1 Jun.2009
The RDA5807SP is a single-chip broadcast FM stereo radio tuner with fully integrated synthesizer, IF selectivity and MPX decoder. The tuner uses the CMOS process, support multi-interface and require the least external component. The package size is SOP16. It is completely adjustment-free. All these make it very suitable for portable devices. The RDA5807SP has a powerful low-IF digital audio processor, this make it have optimum sound quality with varying reception conditions. The RDA5807SP can be tuned to the worldwide frequency band. 1.1 l l Features CMOS single-chip fully-integrated FM tuner Low power consumption O Total current consumption low r than 17.5mA
e
Figure 1-1. RDA5807SP Top View
l l l l l l l l l 1.2 l l l l
Signal dependent mono to stereo blend [Stereo Noise Cancelling (SNC)] Adjustment-free stereo decoder Autonomous search tuning function Bass boost Standby mode Programmable de-emphasis (50/75 s) Directly support 32 resistance loading Integrated LDO regulator O 2.7 to 5.5 V operation voltage SOP16 package Applications Cellular handsets MP3, MP4 players Portable radios PDAs, Notebook PCs
at 3.3V power supply l l Support worldwide frequency band O 76 -108 MHz Digital low-IF tuner O Image-reject down-converter O High performance A/D converter O IF selectivity performed internally l l l l l Autonomous search tuning Support crystal oscillator 32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHz Reference clock 2-wire serial control bus interface Digital auto gain control (AGC) O O O Mono/stereo switch Soft mute High cut
Copyright (c) RDA Microelectronics Inc. 2008. All rights are reserved. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA.
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RDA5807SP FM Tuner V1.1
2
Table of Contents
1
General Description.................................................................................................................................... 1 1.1 Features ......................................................................................................................................... 1 1.2 Applications .................................................................................................................................. 1 Table of Contents ........................................................................................................................................ 2 Functional Description ............................................................................................................................... 3 3.1 FM Receiver ................................................................................................................................. 3 3.2 Synthesizer.................................................................................................................................... 3 3.3 Power Supply................................................................................................................................ 3 3.4 RESET and Control Interface select ............................................................................................. 4 3.5 Control Interface ........................................................................................................................... 4 3.6 GPIO Outputs ............................................................................................................................... 4
2 3
Electrical Characteristics ........................................................................................................................... 5 Receiver Characteristics............................................................................................................................. 6 Serial Interface............................................................................................................................................ 7 6.1 I2C Interface Timing ..................................................................................................................... 7 7 Pins Description ........................................................................................................................................ 8 8 Application Diagram ................................................................................................................................ 10 8.1 Audio Loading Resistance Lower than 32 & SOP16 Application: .......................................... 10 8.1.1 Bill of Materials: ......................................................................................................................... 10 9 Package Physical Dimension.................................................................................................................... 11 10 PCB Land Pattern ................................................................................................................................ 12 11 Change list ................................................................................................................................................. 15 12 Contact Information ................................................................................................................................. 15
4 5 6
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RDA5807SP FM Tuner V1.1
3
Functional Description
Figure 3-1. RDA5807SP FM Tuner Block Diagram 3.1 FM Receiver The DSP core finishes the channel selection, FM demodulation, stereo MPX decoder and output audio signal. The MPX decoder can autonomous switch from stereo to mono to limit the output noise. The DACs convert digital audio signal to analog and change the volume at same time. The DACs has low-pass feature and -3dB frequency is about 30 KHz. 3.2 Synthesizer
The receiver uses a digital low-IF architecture that avoids the difficulties associated with direct conversion while delivering lower solution cost and reduces complexity, and integrates a low noise amplifier (LNA) supporting the FM broadcast band (76 to 108MHz), a quadrature image-reject mixer, a programmable gain control (PGA), a high resolution analog-to-digital converters (ADCs), an audio DSP and a highfidelity digital-to-analog converters (DACs). The LNA has differential input ports (LNAP and LNAN). The LNA default input resistance is 150 Ohm under single or dual input mode. It default input common mode voltage is GND. The limiter prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. The quadrature mixer down converts the LNA output differential RF signal to low-IF, it also has image-reject function. The PGA amplifies the mixer output IF signal and then digitized with ADCs.
The frequency synthesizer generates the local oscillator signal which divide to quadrature, then be used to down convert the RF input to a constant low intermediate frequency (IF). The synthesizer reference clock is 32.768 KHz,12M, 24M, 13M, 26M, 19.2M, 38.4MHz. select by CLK MODE[2:0]
BIT.
3.3
Power Supply
The RDA5807SP integrated one LDO which supplies power to the chip. The external supply voltage range is 2.7-5.5 V.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 3 of 15
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RDA Microelectronics, Inc. 3.4 RESET and Control Interface select
RDA5807SP FM Tuner V1.1
after command byte from MCU, RDA5807SP sends out the first register high byte, then the first register low byte, then the second register high byte, till receives NACK from MCU. MCU gives out ACK for data bytes besides last data byte. MCU gives out NACK for last data byte, and then RDA5807SP will return the bus to MCU, and MCU will give out STOP condition. The RDA5807SP supported two type I2C interface:RDA5807SP Mode and TEA5767 Mode. The different register defined in different interface Mode. Details refer to RDA5807SP Programming Guide. 3.6 GPIO Outputs
The RDA5807SP is RESET itself When VIO is Power up. And also support soft reset. The control interface is select by MODE Pin. The MODE Pin is low ,I2C Interface is select. The MODE Pin is set to VIO, SPI Interface is select. The RDA5807SP could enter into a power-down mode to reduce power consumption. In power-down mode, analog and digital circuitry are both disabled, while maintaining register configuration and keeping control interface active. Details refer to RDA5807SP Programming Guide. 3.5 Control Interface
2
The RDA5807SP supports I C control interface. User could program the chip through the bus. The I C interface is compliant to I C Bus Specification 2.1. It includes two pins: SCLK and 2 SDIO. An I C interface transfer begins with START condition, a command byte and data bytes, each byte has a followed ACK (or NACK) bit, and ends with STOP condition. The command byte includes a 7-bit chip address and an R/W bit. The ACK (or NACK) is always sent out by receiver. When in write transfer, data bytes is written out from MCU, and when in read transfer, data bytes is read out from RDA5807SP. There is no visible 2 register address in I C interface transfers. RDA5807SP always gives out ACK after every byte, and MCU gives out STOP condition when register programming is finished. For read transfer,
2 2
The RDA5807SP has three GPIOs and only used in RDA5807SP Mode. The function of GPIOs could programmed with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0] and I2SEN. If I2SEN is set to low, GPIO pins could be programmed to output low or high or high-Z, or be programmed to output interrupt and stereo indicator with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0]. GPIO2 could be programmed to output a low interrupt (interrupt will be generated only with interrupt enable bit STCIEN is set to high) when seek/tune process completes. GPIO3 could be programmed to output stereo indicator bit ST. Constant low, high or high-Z functionality is available regardless of the state of VDD supplies or the ENABLE bit.
SC K
W S
1SCK
LEFTCHAN NEL
1SCK
RIGHTCHA NNEL
SD
M SB
LSB
M SB
LSB
Figure 3-2. I2S Digital Audio Format
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RDA5807SP FM Tuner V1.1
4
Electrical Characteristics
DC Electrical Specification (Recommended Operation Conditions):
DESCRIPTION Analog Supply Voltage Ambient Temperature CMOS Low Level Input Voltage CMOS High Level Input Voltage CMOS Threshold Voltage MIN 2.7 -20 0 0.7*VDD 0.5*VDD TYP 3.3 27 MAX 5.5 +70 0.3*VDD VDD UNIT V V V V
Table 4-1
SYMBOL
VDD Tamb VIL VIH VTH
Table 4-2
SYMBOL
DC Electrical Specification (Absolute Maximum Ratings):
DESCRIPTION Ambient Temperature Input Current Input Voltage
(1) (1)
MIN -40 -10 -0.3
TYP
MAX +90 +10 VIO+0.3 -20
UNIT C mA V dBm
Tamb IIN VIN Vlna
Notes:
LNA FM Input Level
1. for Pin: SCLK, SDIO, SEN, RST.
Table 4-3
Power Consumption Specification
(VDD = 2.7 to 5.5 V, TA = -25 to 85 , unless otherwise specified) SYMBOL DESCRIPTION Analog Supply Current Analog Powerdown Current CONDITION ENABLE=1 ENABLE=0 TYP 17.5 5 UNIT mA A
I IPD
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RDA5807SP FM Tuner V1.1
5
Receiver Characteristics
Receiver Characteristics
Table 5-1
(VDD = 2.7 to 5.5 V, TA = -25 to 85 C, unless otherwise specified) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
General specifications
Fin Vrf Rin Cin IP3in
FM Input Frequency Sensitivity
1,2,3
7 7
BAND=0 BAND=1 (S+N)/N=26dB
87 76 1.5 150 2 4
108 91 2
MHz MHz V EMF pF dBV dB dB
LNA Input Resistance
4
LNA Input Capacitance Input IP3
1,2
6 -
AGCD=1 m=0.3 200KHz
80 40 45 -
am
S200 VAFL; VAFR
AM Suppression
-
Adjacent Channel Selectivity Left and Right Audio Frequency Output Voltage (Pins LOUT and ROUT)
Volume_dac[3:0] =1111
110
mV
(S+N)/N
Maximum Signal Plus Noise to Noise Ratio
1,2,3,5
54 35
60 0.3
0.5 1
dB dB % dB
SCS
THD
Stereo Channel Separation Audio Total Harmonic Distortion
1,3,6
AOI
RL
Audio Output L/R Imbalance Audio Output Loading Resistance Single-ended 32 -
-
Pins LNAN, LNAP, LOUT, ROUT and NC(22,23)
Vcom_rfin Vcom Vcom_nc
Pins LNAN and LNAP Input Common Mode Voltage Audio Output Common Mode Voltage8 Pins NC (22, 23) Common Mode Voltage 1.2
Float
V
1.25
1.3
V
0.45
0.5
0.55
V
! The NC(22, 23) pins SHOULD BE left floating. Notes: 1. Fin=76 to 108MHz; Fmod=1KHz; de-emphasis=75s; MONO=1; L=R unless noted otherwise; 2. f=22.5KHz; 3. BAF = 300Hz to 15KHz, RBW <=10Hz; 4. |f2-f1|>1MHz, f0=2xf1-f2, AGC disable, Fin=76 to 108MHz; 5. PRF=60dBUV; 6. f=75KHz. 7. Measured at VEMF = 1 m V, f RF = 76 to 108MHz 8. At LOUT and ROUT pins
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RDA5807SP FM Tuner V1.1
6
6.1
Serial Interface
I2C Interface Timing
Table 6-1
I2C Interface Timing Characteristics
(VDD = 2.7 to 5.5 V, TA = -25 to 85 C, unless otherwise specified) PARAMETER SCLK Frequency SCLK High Time SCLK Low Time Setup Time for START Condition Hold Time for START Condition Setup Time for STOP Condition SDIO Input to SCLK Setup SDIO Input to SCLK Hold STOP to START Time SDIO Output Fall Time SDIO Input, SCLK Rise/Fall Time Input Spike Suppression SCLK, SDIO Capacitive Loading Digital Input Pin Capacitance SYMBOL TEST CONDITION MIN 0 0.6 1.3 0.6 0.6 0.6 100 0 1.3 20+0.1Cb 20+0.1Cb TYP MAX 400 900 250 300 50 50 5 UNIT KHz s s s s s ns ns s ns ns ns pF pF
fscl thigh tlow tsu:sta thd:sta tsu:sto tsu:dat thd:dat tbuf tf:out tr:in / tf:in tsp Cb
Figure 6-1. I C Interface Write Timing Diagram
2
Figure 6-2. I2C Interface Read Timing Diagram
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RDA5807SP FM Tuner V1.1
7
Pins Description
1 2 3 4 5 6 7 8
GPIO1 GND GND FMIN GND GND SCLK SDA
GPIO2 GPIO3 GND ROUT LOUT GND VDD RCLK
16 15 14 13 12 11 10 9
RDA5807SP SOP16
Figure 7-1. SOP16 Top View
Table 7-2
RDA5807SP SOP16 Pins Description
PIN DESCRIPTION
SYMBOL
GND FMIN RCLK VDD LOUT,ROUT SCLK SDA GPIO1,GPIO2,GPIO3
2,3,5,6,11,14 4 9 10 12,13 7 8 1,16,15
Ground. Connect to ground plane on PCB FM single input 32.768KHz reference clock input Power supply Right/Left audio output Clock input for serial control bus Data input/output for serial control bus General purpose input/output
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RDA5807SP FM Tuner V1.1
Table 7-2
Internal Pin Configuration
PIN DESCRIPTION
SYMBOL
FMIN
4
RCLK
9
47K
SDIO\SCLK
Sin
SCLK/SDA
7/8
Sout
MN1
GPIO1/GPIO2/GPIO3
1/16/15
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RDA5807SP FM Tuner V1.1
8
8.1
Application Diagram
Audio Loading Resistance Lower than 32 & SOP16 Application:
Figure 8-2. RDA5807SP SOP16 FM Tuner Application Diagram
8.1.1
Bill of Materials:
VALUE DESCRIPTION SUPPLIER
COMPONENT
U1 J1 L1/C2 C4,C5 C1 F1/F2
RDA5807SP SOP16
Broadcast FM Radio Tuner Common 32 Resistance Headphone
RDA
100nH/24pF 125F 24nF 1.5K@100MHz
LC Chock for LNA Input Audio AC Couple Capacitors Power Supply Bypass Capacitor FM Band Ferrite
Murata Murata Murata Murata
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RDA5807SP FM Tuner V1.1
9
Package Physical Dimension
Figure 9-1 illustrates the package details for the RDA5807SP. The package is lead-free and RoHS-compliant.
Symbol
Dimensions In Millimeters Min Max 1.750 0.250 1.550 0.510 0.250 10.200 4.000 6.200 1.270(BSC) 1
Dimensions In Inches Min 0.053 0.004 0.053 0.013 0.007 0.386 0.150 0.228 0.050(BSC) 7
Max 0.069 0.010 0.061 0.020 0.010 0.402 0.157 0.244
A A1 A2 b c D E E1 e L
1.350 0.100 1.350 0.330 0.170 9.800 3.800 5.800
1
7
0.400
1.270
0.016
0.050
Figure 9-1. 16 PIN SOP
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RDA5807SP FM Tuner V1.1
10 PCB Land Pattern
Figure 10-1.Classification Reflow Profile
Profile Feature Average Ramp-Up Rate (TSmax to Tp) Preheat -Temperature Min (Tsmin) -Temperature Max (Tsmax) -Time (tsmin to tsmax) Time maintained above: -Temperature (TL) -Time (tL) Peak /Classification Temperature(Tp) Time within 5 oC of actual Peak Temperature (tp) Ramp-Down Rate Time 25 oC to Peak Temperature
Sn-Pb Eutectic Assembly 3 oC/second max.
Pb-Free Assembly 3 oC/second max.
100 oC 100 oC 60-120 seconds
150 oC 200 oC 60-180 seconds
183 oC 60-150seconds See Table-II 10-30 seconds 6 oC/second max. 6 minutes max. Table-I Classification Reflow Profiles
217oC 60-150 seconds See Table-III 20-40 seconds 6 oC/seconds max. 8 minutes max.
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RDA5807SP FM Tuner V1.1
Package Thickness
Volume mm3 <350
Volume mm3 350 225 + 0/-5 o C 225 + 0/-5 o C
2.5mm 2.5mm
240 + 0/-5 o C 225 + 0/-5 o C
Table - II SnPb Eutectic Process - Package Peak Reflow Temperatures Package Thickness 1.6mm 1.6mm - 2.5mm 2.5mm Volume mm3 350 260 + 0 o C * 260 + 0 o C * 250 + 0 o C * Volume mm3 350-2000 260 + 0 o C * 250 + 0 o C * 245 + 0 o C * Volume mm3 2000 260 + 0 o C * 245 + 0 o C * 245 + 0 o C *
*Tolerance : The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature(this mean Peak reflow temperature + 0 o C. For example 260+ 0 o C ) at the rated MSL Level. Table - III Pb-free Process - Package Classification Reflow Temperatures Note 1: All temperature refer topside of the package. Measured on the package body surface. Note 2: The profiling tolerance is + 0 capability)whatever
o
C, - X
o
C (based on machine variation
is required to control the profile process but at no time will it exceed - 5 o C. The producer assures process compatibility at the peak reflow profile temperatures defined in Table -III. Note 3: Package volume excludes external terminals(balls, bumps, lands, leads) and/or non integral heat sinks. Note 4: The maximum component temperature reached during reflow depends on package the thickness and volume. The use of convection reflow processes reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD package may sill exist. Note 5: Components intended for use in a "lead-free" assembly process shall be evaluated using the "lead free" classification temperatures and profiles defined in Table-I II III whether or not lead free.
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RDA5807SP FM Tuner V1.1
RoHS Compliant
The product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE), and are therefore considered RoHS compliant.
ESD Sensitivity
Integrated circuits are ESD sensitive and can be damaged by static electricity. Proper ESD techniques should be used when handling these devices.
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